1. Field of the Invention
The present invention relates to an apparatus and a method for receiving a data packet; and, more particularly, to an apparatus and a method for receiving a data packet by maximally utilizing a bandwidth of an input/output channel and a network communication.
2. Description of Related Arts
FIG. 1 is a diagram showing a format of a packet generally used in conventional data communication in a computer network or various data input/output computer devices. Referring to FIG. 1, the packet is generally constructed with multiple fields such as header, data and a cyclic redundancy check CRC. For data communication, the packet is divided into a plurality of data units according to a data communication method. The data unit is a smallest unit for transmitting the packet and it is usually 1–4 bytes of data. Each of the data units is individually transmitted and received. For detecting any errors included in the packet, the packet is inspected by checking a redundancy bit included in each of the data units to calculate a CRC value at a receiver side. The calculated CRC value of the receiver side is compared to a CRC value of a transmitter side. If they are different then an error occurred. Therefore, all data units of the packet have to have arrived for calculating the CRC value. After inspecting all the data units, if there are any errors, the packet is deleted. If there are no errors, the packet is passed to the higher layer for the next processing of the packet.
FIG. 2A is a diagram illustrating a conventional apparatus for receiving data packets. Referring to FIG. 2A, the conventional data packet receiver includes a memory & controller 210 for temporally storing received data units 1 and outputting stored data units to a multiplexer 230 according to an error detection signal 3; an inspection logic circuit 220 for performing an error checking process on stored data units 2 and generating the error detection signal 3 to the memory & controller 210, a multiplexer 230 for distributing the received data packet 4 from the memory & controller 210 to a plurality of first-in-first out memories (FIFO) 241 to 244 where the plurality of first-in first-out FIFO Memories 241 to 244 store the data packet from the multiplexer 230 and output the data packets to a higher layer. The higher layer represents the next step of processing the received packet.
Detailed operations of the conventional data packet receiver are explained hereinafter.
The received data packets are stored at the memory & controller 210 and the stored data packet is inspected for detecting error by the inspection logic circuit 220. If there is no error found in the stored data packet, the stored data packet is passed to the higher layer through the FIFO memories 241 to 244.
FIG. 2B is a flowchart for showing a conventional method for receiving a data packet. Referring to FIG. 2B, a data packet consists of multiple data units. A data unit is received at step S201. If the received data unit is not the last data unit of a corresponding data packet at step S202, then the received data unit is stored in a temporary memory space at step S203, and the next data unit is received at step S201. If the received data unit is the last data unit of the data packet at step S202, a field of a packet header is appropriately processed at step S204. After processing the packet header, a field of data is processed and redundancy bits included in each of the data units are processed for detecting error at step S205. At step S206, the cyclic redundancy check code in the last field of the packet and redundancy bits in every data unit are compared, and it is determined whether an error is included in the packet according to a result of the comparison at step S207. If an error is found the packet is dumped at step S208 and if an error is not found the packet is inputted to the FIFO memory at step S209 and passed to the higher layer. The packet is processed at step S210. If there is no error found at step S211, the packet is processed again at step S210, and if there is an error found, the packet is dumped at step S212.
As mentioned above, the conventional method for receiving the data packet and inspecting the data packet for finding errors are time consuming processes since every data unit of the packet needs to have arrived before starting to inspect, and also requires plenty of space for temporary storing the data units of the data packet before finding an error in the data packet.
Therefore, a size of memory for buffering or storing the received data packet needs to be increased in order to process high-speed incoming data packets of a next generation standard of data network communication and high-speed input/output devices, such as InfiniBand, Giga-Bit Ethernet, a RapidIO and PCI Express. By increasing the memory size, a cost is also increased and it requires a complicated control mechanism. Furthermore, electric power consumption is also increased.
FIG. 3 is a block diagram illustrating a plurality of FIFO memories 241 to 244 equipped in the conventional data packet receiver. Referring to FIG. 3, the conventional FIFO memories 241 to 244 include a dual-port SRAM 320 and a FIFO memory controller 310. The FIFO memory controller 310 generates an empty signal or a full signal according to data address state of dual port SRAM 320. The FIFO memory controller 310 generates and outputs a write address and activates a write_allow signal when the full signal is inactivated and a write_enable_in signal is activated. Also, the FIFO memory controller 310 generates and outputs a read address when a read_enable_in signal is activated and the empty signal is inactivated. The dual port SRAM 320 stores data at the write address received from the FIFO memory controller 310 when the write_allow signal is activated. If the read_allow signal is activated, the dual port SRAM 320 outputs data stored at the read address received from the FIFO memory controller 310.
As mentioned above, the conventional data packet receiver using FIFO memory needs to receive all data units of one packet before inputting the received data units to FIFO memory. Because the conventional FIFO memory cannot dump one specific data unit stored during receiving other data units, the received packet has to be inspected for finding errors before inputting the packet to the FIFO memory. For overcoming the above-mentioned method, an enhanced FIFO memory circuit is developed. The enhanced FIFO memory stores packets into a register file by assigning a store-address to each packet.
A huge size of memory space and registers, however, are also required in the enhanced FIFO memory in case of continuously receiving a great quantity of minimum size packets. Therefore, complexity is increased for controlling the memory and distributing memory space.